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vishay siliconix si9130 document number: 70190 s11-0975-rev. g, 16-may-11 www.vishay.com 1 not recommended for new designs, please refer to si786 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pin-programmable dual cont roller - portable pcs features ? fixed 5 v and programmable 3.3 v, 3.45 v, or 3.6 v step-down converters ? less than 500 a quiescent current per converter ? 25 a shutdown current ? 5.5 v to 30 v operating range description the si9130 pin-programmable dual controller for portable pcs is a pin-programmable version of the si786 dual-output power supply controller for notebook computers. the buck controllers provide 5 v an d a pin-programmable output delivering 3.3 v, 3.45 v, or 3.6 v. the circuit is a system level integration of two step-down controllers and micropower 5 v and 3.3 v linear regulators. the controllers perform high efficiency conversion of the battery pack energy (typically 12 v) or the output of an ac to dc wall converter (typically 18 v to 24 v dc) to 5 v and 3.3 v system supply voltages. the micropower linear regulator can be used to keep power management and back-up circuitry alive during the shutdown of the step-down converters. a complete power conversion and management system can be implemented with the si9130 pin-programmable dual controller for portable pcs, an inexpensive linear regulator, the si9140 smp controller for high performance processor power supplies, five si4410 n-channel trenchfet ? power mosfets, one si4435 p-channel trenchfet power mosfet, and two si9712 pc card (pcmcia) interface switches. the si9130 is available in both standard and lead (pb)-free 28-pin ssop packages and specified to operate over the commercial (0 c to 70 c ) and extended commercial (- 10 c to 90 c) temperature ranges. see ordering information for corresponding part numbers. functional block diagram si9130 shutdown 5 v on/off 3.3 v on/off sync power section 3.3 v 5 v p memory peripherals 5.5 v to 30 v
www.vishay.com 2 document number: 70190 s11-0975-rev. g, 16-may-11 vishay siliconix si9130 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. device mounted with all leads soldered or welded to pc board. b. derate 9.52 mw/c above 70 c. exposure to absolute maximum rating conditions for extended periods may affect device reliability. stresses above absolute maxi mum rating may cause permanent damage. functional operation at conditions other than the operat ing conditions specified is not implied. only one absolute maxi mum rating should be applied at any one time. absolute maximum ratings parameter limit unit v+ to gnd - 0.3 to 36 v pgnd to gnd 2 v l to gnd - 0.3 to 7 bst 3 , bst 5 to gnd - 0.3 to 36 lx 3 to bst 3 - 7 to 0.3 lx 5 to bst 5 - 7 to 0.3 inputs/outputs to gnd (3.45 adj, 3.6 adj, shdn , on 5 , ref, ss 5 , cs 5 , fb 5 , sync, cs 3 , fb 3 , ss 3 , on 3 ) - 0.3, (v l + 0.3) dl 3 , dl 5 to pgnd - 0.3, (v l + 0.3) dh 3 to lx 3 - 0.3 (bst 3 + 0.3) dh 5 to lx 5 - 0.3 (bst 5 + 0.3) ref, v l short to gnd momentary ref current 20 ma v l current 50 continuous power dissipation (t a = 70 c) a 28-pin ssop b 762 mw operating temperature range: si9130cg 0 to 70 c si9130lg - 10 to 90 lead temperature (soldering, 10 sec) 300 specifications parameter specific test conditions v+ = 15 v, i vl = i ref = 0 ma, shdn = on 3 = on 5 = 5 v other digital input levels 0 v or 5 v, t a = t min to t max limits unit min. a typ. b max. a 3.3 v and 5 v step-down controllers input supply range 5.5 30 v fb 5 output voltage 0 mv < (cs 5 - fb 5 ) < 70 mv, 6 v < v + < 30 v (includes load and line regulation) 4.80 5.08 5.20 fb 3 output voltage 0 mv < (cs 3 - fb 3 ) < 70 mv 6 v < v + < 30 v (includes load and line regulation) 3.6 adj = 3.45 adj = open 3.17 3.35 3.46 3.6 adj = open 3.45 adj = gnd 3.32 3.50 3.60 3.6 adj = gnd 3.45 adj = open 3.46 3.65 3.75 load regulation either controller (cs_ to fb_ = 0 to 70 mv) 2.5 % line regulation either controller (v+ = 6 to 30) 0.03 %/v current-limit voltage cs 3 - fb 3 or cs 5 - fb 5 80 100 120 mv ss 3 /ss 5 source current 2.5 4.0 6.5 a ss 3 /ss 5 fault sink current 2ma internal regulator and reference v l output voltage on 5 = on 3 = 0, 5.5 < v+ < 30 0 ma < i l < 25 ma 4.5 5.5 v v l fault lockout voltage falling edge, hysteresis = 1 % 3.6 4.2
document number: 70190 s11-0975-rev. g, 16-may-11 www.vishay.com 3 vishay siliconix si9130 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. the algebraic convention whereby the most negative value is a minimu m and the most positive a maximum. b. typical values are for design aid only, not guaranteed nor subject to production testing. c. the main switching outputs track the reference voltage. loading the reference reduces the main outputs slightly according to the closed-loop gain (av cl ) and the reference voltage load-regulation error. av cl for the 3.3 v supply is unity gain. av cl for the 5 v supply is 1.54. d. since the reference uses v l as its supply, its v+ line regu lation error is insignificant. specifications parameter specific test conditions v+ = 15 v, i vl = i ref = 0 ma, shdn = on 3 = on 5 = 5 v other digital input levels 0 v or 5 v, t a = t min to t max limits unit min. a typ. b max. a internal regulator and reference v l /fb 5 switchover voltage rising edge of fb 5 , hysteresis = 1 % 4.2 4.7 v ref output voltage no external load c 3.24 3.36 ref fault lockout voltage falling edge 2.4 3.2 ref load regulation 0 ma < i l < 5 ma d 30 75 mv v+ shutdown current shdn = on 3 = on 5 = 0 v, v+ = 30 v 25 40 a v+ standby current on 3 = on 5 = 0 v, v+ = 30 v 70 110 quiescent power consumption (both pwm controllers on) fb 5 = cs 5 = 5.25 v fb 3 = cs 3 = 3.5 v 5.5 8.6 mv v+ off current fb 5 = cs 5 = 5.25 v, v l switched over to fb 5 30 60 a oscillator and inputs/outputs oscillator frequency sync = 3.3 v 270 300 330 khz sync = 0 v, 5 v 170 200 230 sync high pulse width 200 ns sync low pulse width 200 sync rise/fall time not tested 200 oscillator sync range 240 350 khz maximum duty cycle sync = 3.3 v 89 92 % sync = 0 v, 5 v 92 95 input low voltage shdn , on 3 , on 5 sync 0.8 v input high voltage shdn , on 3 , on 5 2.4 sync v l - 0.5 input current shdn , on 3 , on 5 , v in = 0 v, 5 v 1 a dl 3 /dl 5 sink/source current v out = 2 v 1 a dh 3 /dh 5 sink/source current bst 3 - lx 3 = bst 5 - lx 5 = 4.5 v, v out = 2 v 1 dl 3 /dl 5 on-resistance high or low 7 ? dh 3 /dh 5 on-resistance high or low bst 3 - lx 3 = bst 5 - lx 5 = 4.5 v 7
www.vishay.com 4 document number: 70190 s11-0975-rev. g, 16-may-11 vishay siliconix si9130 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c unless noted) efficiency vs. 5 v output current, 200 khz efficiency vs. 3.3 v output current, 200 khz quiescent supply current vs. supply voltage 50 60 70 80 90 100 0.001 0.1 1 10 0.01 sync = 0 v, 3.3 v off 5 v output current (a) ) % ( y c n e i c i f f e v in = 6 v v in = 30 v v in = 15 v 50 60 70 80 90 100 0.001 0.1 1 10 0.01 3.3 v output current (a) ) % ( y c n e i c i f f e sync = 0 v, 5 v on v in = 6 v v in = 30 v v in = 15 v 0 5 10 15 20 25 30 0 6 12 18 24 30 supply voltage (v) ) a m ( t n e r r u c y l p p u s t n e c s e i u q on 3 = on 5 = high efficiency vs. 5 v output current, 300 khz efficiency vs. 3.3 v output current, 300 khz standby supply current vs. supply voltage 50 60 70 80 90 100 0.001 0.1 1 10 0.01 5 v output current (a) ) % ( y c n e i c i f f e 3.3 v off v in = 6 v v in = 30 v v in = 15 v 50 60 70 80 90 100 0.001 0.1 1 10 0.01 3.3 v output current (a) ) % ( y c n e i c i f f e 5 v on v in = 6 v v in = 30 v v in = 15 v 0.0 0.1 0.2 0.3 0.4 0.5 0 6 12 18 24 30 supply voltage (v) on 3 = on 5 = 0 v ) a m ( t n e r r u c y l p p u s y b d n a t s
document number: 70190 s11-0975-rev. g, 16-may-11 www.vishay.com 5 vishay siliconix si9130 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c unless noted) shutdown supply current vs. supply voltage (a) t n e r r u c y l p p u s n w o d t u h s 0 25 50 75 100 0 6 12 18 24 30 shdn = 0 v supply voltage (v) minimum v in to v out differential vs. 5 v output current ) v ( l a i t n e r e f f i d v m u m i m i m n i v o t t u o 0.0 0.2 0.4 0.6 0.8 1.0 0.001 0.1 1 10 0.01 5 v output current (a) 300 khz 5 v output still regulating 200 khz switching frequency vs. load current 0.1 1.0 10.0 100.0 1000.0 0.1 10 100 1000 1 load current (ma) ) z h k ( y c n e u q e r f g n i h c t i w s sync = ref (300 khz) on 3 = on 5 = 5 v 5 v, v in = 7.5 v 5 v, v in = 30 v 3.3 v, v in = 7.5 v pulse-skipping waveforms 200 s/div i load = 100 ma v in = 10 v 5 v output 50 mv/div 2 v/div pulse-width modulation mode waveforms 500 ns/div 5 v output current = 1 a v in = 16 v 5 v output 50 mv/div lx 10 v/div
www.vishay.com 6 document number: 70190 s11-0975-rev. g, 16-may-11 vishay siliconix si9130 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c unless noted) 5 v load-transient response 5 v line-transient response, rising 3.3 v line-transient response, rising 200 s/div v in = 15 v 5 v output 50 mv/div 3 a load current 0 a 20 s/div i load = 2 a 5 v output 50 mv/div v in , 10 to 16 v 2 v/div 20 s/div i load = 2 a 3.3 v output 50 mv/div v in , 10 to 16 v 2 v/div 3.3 v load-transient response 5 v line-transient response, falling 3.3 v line-transient response, falling 200 s/div v in = 15 v 3.3 v output 50 mv/div 3 a load current 0 a 20 s/div i load = 2 a 5 v output 50 mv/div v in , 16 to 10 v 2 v/div 20 s/div i load = 2 a 3.3 v output 50 mv/div v in , 16 to 10 v 2 v/div
document number: 70190 s11-0975-rev. g, 16-may-11 www.vishay.com 7 vishay siliconix si9130 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pin configuration and description cs 3 fb 3 ss 3 ssop-28 dh 3 on 3 lx 3 nc bst 3 nc nc 3.6adj dl 3 v+ v l top view 25 26 27 28 2 3 4 1 22 23 24 5 6 7 3.45adj fb 5 gnd pgnd ref dl 5 sync bst 5 shdn on 5 ss 5 lx 5 dh 5 cs 5 18 19 20 21 9 10 11 8 15 16 17 12 13 14 ordering information standard part number lead (pb)-free part number temperature range v out si9130cg 0 to 70 c 5 v and 3.3 v 3.45 v or 3.6 v SI9130CG-T1 SI9130CG-T1-e3 si9130lg - 10 to 90 c si9130lg-t1 si9130lg-t1-e3 demo board temperature range board type si9130db 0 to 70 c surface mount pin description pin symbol description 1cs 3 current-sense input for 3.3 v buck cont roller - this pins over current th reshold is 100 mv with respect to fb 3 . 2ss 3 soft-start input for 3.3 v. connect capacitor from ss 3 to gnd. 3on 3 on/off logic input disables the 3.3 v buck controller. connect directly to v l for automatic turn-on. 4 nc not internally connected. 5 nc not internally connected. 6 nc not internally connected. 7 3.6 adj control input to select 3.6 v output. see voltage selection table for input and output combinations. 8 3.45 adj control input to select 3.45 v output. see voltage selection table for input and output combinations. 9 gnd analog ground. 10 ref 3.3 v reference output. supplies external loads up to 5 ma. 11 sync oscillator control/synchronization input. co nnect capacitor to gnd, 1 f/ma output or 0.22 f minimum. for external clock synchronization, a rising edge starts a new cycle to start. to use internal 200 khz oscillator, connect to v l or gnd. for 300 khz oscillator, connect to ref. 12 shdn shutdown logic input, active low. connect to v l for automatic turn-on. the 5 v v l supply will not be disabled in shutdown allowing connection to shdn . 13 on 5 on/off logic input disables the 5 v buck controller. connect to v l for automatic turn-on. 14 ss 5 soft-start control input for 5 v buck controller. connect capacitor from ss 5 to gnd. 15 cs 5 current-sense input for 5 v buck cont roller - this pins over current threshold is 100 mv referenced to fb 3 . 16 dh 5 gate-drive output for the 5 v supply high-side n- channel mosfet. 17 lx 5 inductor connection for the 5 v supply. 18 bst 5 boost capacitor connecti on for the 5 v supply. 19 dl 5 gate-drive output for the 5 v supply rectifying n-channel mosfet. 20 pgnd power ground. 21 fb 5 feedback input for the 5 v buck controller. 22 v l 5 v logic supply voltage for internal circuitry - able to source 5 ma external loads. v l remains on with valid voltage at v+. 23 v+ supply voltage input. 24 dl 3 gate-drive output for the 3.3 v supply rectifying n-channel mosfet. 25 bst 3 boost capacitor connecti on for the 3.3 v supply. 26 lx 3 inductor connection for the 3.3 v supply. 27 dh 3 gate-drive output for the 3.3 v supply high-side n- channel mosfet. 28 fb 3 feedback input for the 3.3 v buck controller.
www.vishay.com 8 document number: 70190 s11-0975-rev. g, 16-may-11 vishay siliconix si9130 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 description of operation the si9130 is a dual step-down converter, which takes a 5.5 v to 30 v input and supplies power via two pwm controllers (see figure 1). these 5 v and 3.3 v supplies run on an optional 300 khz or 200 khz internal oscillator, or an external sync signal. amount of output current is limited by external components, but can deliver greater than 6 a on either supply. as well as t hese two main buck controllers, additional loads can be driven from two micropower linear regulators, one 5 v (v l ) and the other 3.3 v (ref) - see figure 2. these supplies are each rated to deliver 5 ma. if the linear regulator circuits fall out of regulation, both buck controllers are shut down. 3.3 v pwm voltage selection (pins 3.45 adj, 3.6 adj) the voltage at this output can be selected to 3.3 v, 3.45 v or 3.6 v, depending on the configuration of pins 3.45 adj and 3.6 adj. leaving both pins open results in 3.3v nominal output. grounding pin 3.45 adj while leaving 3.6 adj open delivers 3.45 v nominal outpu t. grounding 3.6 adj while leaving 3.45 adj open sets a 3.6 v nominal output. voltage selection table input output 3.45 adj 3.6 adj fb 3 open open 3.3 v gnd open 3.45 v open gnd 3.6 v figure 1. si9130 application circuit cs 3 fb 3 ss 5 si9130 dh 5 on 3 lx 3 bst 3 3.6adj dl 5 v+ v l 17 16 18 22 25 27 26 23 21 15 19 24 1 28 3.45adj fb 5 gnd pgnd ref dl 3 sync bst 5 shdn on 5 ss 3 lx 5 dh 3 cs 5 8 14 3 13 12 2 20 7 11 9 10 n3 d1 d1fs4 (note 1) n3 d1 d1fs4 (note 1) input 5.5 v to 30 v + 3.3 v at 3 a c7 150 f c12 150 f r1 25 m l1 10 h n1 n2 d2a 1n4148 d2b 1n4148 c5 0.1 f c4 0.1 f c1 22 f c10 22 f 4.7 f + 5 v at 5 ma + 5 v at 3 a c6 330 f r2 25 m l2 10 h c9 0.01 f c8 0.01 f + 3.3 v on/off + 5 v on/off shutdown osc sync 3.45 v voltage adjust 3.6 v voltage adjust + 3.3 v at 5 ma c3 1 f note 1: use short, kelvin-connected pc board traces placed very close to one another. 0.1 f 100
document number: 70190 s11-0975-rev. g, 16-may-11 www.vishay.com 9 vishay siliconix si9130 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 3.3 v switching supply the 3.3 v supply is regul ated by a current-mode pwm controller in conjunction with several externals: two n-channel mosfets, a rect ifier, an inductor and output capacitors (see figure 1). the gate drive supplied by dh 3 needs to be greater than v l , so it is provided by the bootstrap circuit consisting of a 100 nf capacitor and diode connected to bst 3 . a low-side switching mosfet connected to dl 3 increases efficiency by reducing the voltage across the rectifier diode. a low value sense resistor in series with the inductor sets the maximum current limit, to disallow current overloads at power-on or in short-circuit situations. the soft-start feature on the si9130 is capacitor programmable; pin ss 3 functions as a constant current source to the external capacitor connected to gnd. excess currents at power-on are avoided, and power-supplies can be sequenced with different turn-on delay times by selecting the correct capacitor value. 5 v switching supply the 5 v supply is regulated by a current-mode pwm controller which is nearly the same as the 3.3 v output. the dropout voltage across the 5 v supply, as shown in the schematic in figure 1, is 400 mv (typ) at 2 a. if the voltage at v+ falls, nearing 5 v, the 5 v supply will lower as well, until the v l linear regulator output falls below the 4 v undervoltage lockout threshold. below this threshold, the 5 v controller is shut off. the frequency of both pwm cont rollers is set at 300 khz when the sync pin is tied to ref. connecting sync to either gnd or v l sets the frequency at 200 khz. figure 2. si9130 block diagram + 5 v ldo linear regulator + 3.3 v reference on 300 khz/200 khz oscillator on 3.3 v pwm controller (see figure 3) 5 v pwm controller (see figure 3) standby fb 3 cs 3 bst 3 dh 3 lx 3 dl 3 ss 3 on 3 on 5 pgnd fb 5 cs 5 bst 5 dh 5 lx 5 dl 5 ss 5 v+ v l ref shdn sync 4.5 v 4 v 2.8 v on on 3.6adj 3.45adj
www.vishay.com 10 document number: 70190 s11-0975-rev. g, 16-may-11 vishay siliconix si9130 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 3.3 v and 5 v swit ching controllers each pwm controller on the si9130 is identical with the exception of the preset output voltages. the controllers only share three functional blocks (see figure 3): the oscillator, the voltage reference (ref) and the 5 v logic supply (v l ). the 3.3 v and 5 v controllers are independently enabled with pins on 3 and on 5 , respectively. the pwms are a direct- summing type, without the typica l integrating error amplifier along with the phase shift which is a side effect of this type of topology. feedback compensation is not needed, as long as the output capacitance and its esr requirements are met, according to the design considerations section of this data sheet. the main pwm comparator is an open loop device which is comprised of three comparators summing four signals: the feedback voltage error signal, current sense signal, slope- compensation ramp and voltage reference as shown in figure 3. this method of contro l comes closer to the ideal of maintaining the output volt age on a cycle-by-cycle basis. when the load demands high current levels, the controller is in full pwm mode. every cycle fr om the oscillator asserts the output latch and drives the gate of the high-side mosfet for a period determined by th e duty cycle (approximately v out /v in x 100 %) and the frequency. the high-side switch turns off, setting the synchronous rectifier latch and 60 ns later, the rectifier mosfet turns on. the low-side switch stays on un til the start of the next clock figure 3. si9130 controller block diagram 60 khz lpf cs_ osc 1x r s q r s q level shift level shift shoot- through control fb_ bst_ dh_ lx_ v l dl_ pgnd current limit 0 mv to 100 mv synchronous rectifier control 1r 30r v l 4 a 3.3 v minimum current (pulse-skipping mode) 25 mv ref, 3.3 v (or internal 5 v reference) ss_ on_ summing comparator slope comp
document number: 70190 s11-0975-rev. g, 16-may-11 www.vishay.com 11 vishay siliconix si9130 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 cycle in continuous mode, or until the inductor current becomes positive again, in discontinuous mode. in over- current situations, where the inductor current is greater than the 100 mv current-limit thre shold, the high-side latch is reset and the high-side gate drive is shut off. during low-current load require ments, the inductor current will not deliver the 25 mv minimum current threshold. the minimum current comparator signals the pwm to enter pulse-skipping mode when the threshold has not been reached. pulse-skipping mode skips pulses to reduce switching losses, the losses which decrease efficiency the most at light load. entering this mode causes the minimum current comparator to reset the high-side latch at the beginning of each oscillator cycle. soft-start to slowly bring up the 3.3 v and 5 v supplies, connect capacitors from ss 3 and ss 5 to gnd. asserting on 3 or on 5 starts a 4 a constant current source to charge these capacitors to 4 v. as the voltage on these pins ramps up, so does the current limit comparator threshold, to increase the duty cycle of the mosfets to their maximum level. if on 3 or on 5 are left low, the respective capacitor is discharged to gnd. leaving the ss 3 or ss 5 pins open will cause either controller to reach the terminal over-current level within 10 s. soft start helps prevent current spikes at turn-on and allows separate supplies to be delayed using external programmability. synchronous rectifiers synchronous rectification replaces the schottky rectifier with a mosfet, which can be controlled to increase the efficiency of the circuit. when the high-side mosfet is switched off, the inductor will try to maintain its current flow, inverting the inductor?s polarity. the path of current then becomes the circuit made of the schottky diode, induct or and load, which will charge the output capacitor. the diode has a 0.5 v forward voltage drop, which contributes a sign ificant amount of power loss, decreasing efficiency. a low-side switch is placed in parallel with the schottky diode and is turned on just after the diode begins to conduct. because the r ds(on) of the mosfet is low, the i*r voltage drop will not be as large as the diode, which increases efficiency. the low-side rectifier is shut off when the inductor current drops to zero. shoot-through current is the result when both the high-side and rectifying mosfets are turned on at the same time. break-before-make timing internal to the si9130 manages this potential problem. during the time when neither mosfet is on, the schottky is conducting, so that the body diode in the low-side mosfet is not forced to conduct. synchronous rectification is always active when the si9130 is powered-up, regardless of the operational mode. gate-driver boost the high-side n-channel drive is supplied by a flying- capacitor boost circuit (see figure 4). the capacitor takes a charge from v l and then is connected from gate to source of the high-side mosfet to pr ovide gate enhancement. at power-up, the low-side mosfet pulls lx_ down to gnd and charges the bst_ capacito r connected to 5 v. during the second half of the oscillator cycle, the controller drives the gate of the high-side mo sfet by internally connecting node bst_ to dh_. this supplies a voltage 5 v higher than the battery voltage to the gat e of the high-side mosfet. oscillations on the gates of the high-side mosfet in discontinuous mode are a natural occurrence caused by the lc network formed by the i nductor and stray capacitance at the lx_ pins. the negative si de of the bst_ capacitor is connected to the lx_ node, so ringing at the inductor is translated through to the gate drive. figure 4. boost supply for gate drivers level translator dh_ bst_ lx_ dl_ v l pwm v l v l battery input
www.vishay.com 12 document number: 70190 s11-0975-rev. g, 16-may-11 vishay siliconix si9130 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 operational modes pwm mode the 3.3 v and 5 v buck controllers operate in continuous- current pwm mode when the load demands more than approximately 25 % of the maximum current (see typical curves). the duty cycle can be approximated as duty_cycle = v out /v in . in this mode, the inductor current is continuous; in the first half of the cycle, the current slopes up when the high-side mosfet conducts and then, in the second half, slopes back down when the inductor is providing energy to the output capacitor and load. as current ent ers the inductor in the first half-cycle, it is also continuing through to the load; hence, the load is receiving continuous cu rrent from the inductor. by using this method, output ripple is minimized and smaller form-factor inductors can be us ed. the output capacitor?s esr has the largest effect on output ripple. it is typically under 50 mv; the worst case condition is under light load with higher input battery voltage. pulse-skipping mode when the load requires less than 25 % of its maximum, the si9130 enters a mode which drives the gate for one clock cycle and skips the majority of the remaining cycles. pulse- skipping mode cuts down on the switching losses, the dominant power consumer at low current levels. in the region between pulse-skipping mode and pwm mode, the controller may transition between the two modes, delivering spurts of pulses. this may cause the current waveform to look irregular, but w ill not overly affect the ripple voltage. even in this transitioning mode efficiency will stay high. current limit the current through an exter nal resistor, is constantly monitored to protect against over-current. a low value resistor is placed in series with the inductor. the voltage across it is measured by connecting it between cs_ and fb_. if this voltage is lar ger than 100 mv, the high-side mosfet drive is shut down. eliminating over-currents protects the mosfet, the load and the power source. typical values for the sense resistors with a 3 a load will be 25 m ? . oscillator and sync there are two ways to set the si9130 oscillator frequency: by using an external sync signal, or using the internal oscillator. the sync pin can be driven with an external cmos level signal with frequency from 240 khz and 350 khz to synchronize to the internal oscillator. tying sync to either v l or gnd sets the frequency to 200 khz and to ref sets the frequency to 300 khz. operation at 300 khz is typically used to minimize output passive component sizes. sl ower switching speeds of 200 khz may be needed for lower input voltages. internal v l and ref a 5 v linear regulator supplies power to the internal logic circuitry. the regulator is available for external use from pin v l , able to source 5 ma. a 4.7 f capacitor should be connected between v l and gnd. to increase efficiency, when the 5 v switching supply has voltage greater than 4.5 v, v l is internally switched over to the output of the 5 v switching supply and the linear regulator is turned off. the 5 v linear regulator provides power to the internal 3.3 v bandgap reference (ref). the 3.3 v reference can supply 5 ma to an external load, connected to pin ref. between ref and gnd connect a capacitor, 0.22 f plus 1 f per ma of load current. the switching outputs will vary with the reference; therefore, placing a load on the ref pin will cause the main outputs to decrease slightly, within the specified regulation tolerance. v l and ref supplies stay on as long as v+ is greater than 4.5 v, even if the switchin g supplies are not enabled. this feature is necessary when using the micropower regulators to keep memory alive during shutdown. both linear regulators can be connected to their respective switching supply outputs. for example, ref would be tied to the output of the 3.3 v and v l to 5 v. this will keep the main supplies up in standby mode, provided that each load current in shutdown is not larger than 5 ma. fault protection the 3.3 v and 5 v switching controllers are shut down when one of the linear regulators dr ops below 85 % of its nominal value; that is, shut down will occur when v l <4.0vorref<2.8v.
document number: 70190 s11-0975-rev. g, 16-may-11 www.vishay.com 13 vishay siliconix si9130 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 design considerations inductor design three specifications are r equired for inductor design: inductance (l), peak inductor current (i lpeak ), and coil resistance (r l ). the equation for co mputing inductance is: where: v out = output voltage (3.3 v or 5 v); v in(max) = maximum input voltage (v); f = switching frequency, normally 300 khz; i out = maximum dc load current (a); lir = ratio of inductor peak-to-peak ac current to average dc load current, typically 0.3. when lir is higher, smaller inductance values are acceptable, at the expense of increased ripple and higher losses. the peak inductor current (i lpeak ) is equal to the steady- state load current (i out ) plus one half of the peak-to-peak ac current (i lpp ). typically, a designer will select the ac inductor current to be 30 % of the steady-state current, which gives i lpeak equal to 1.15 times i out . the equation for computing peak inductor current is: output capacitors the output capacitors determine loop stability and ripple voltage at the output. in order to maintain stability, minimum capacitance and maximum esr requirements must be met according to the following equations: and, where: c f = output filter capacitance (f) v ref = reference voltage, 3.3 v; v out = output voltage, 3.3 v or 5 v; r cs = sense resistor ( ? ); gbwp = gain-bandwidth product, 60 khz; esr cf = output filter capacitor esr ( ? ). both minimum capacitance and maximum esr requirements must be met. in order to get the low esr, a capacitance value of two to three times greater than the required minimum may be necessary. the equation for output ripple in continuous current mode is: the equations for capacitive and resistive components of the ripple in pulse-skipping mode are: the total ripple, v out(rpl) , can be approximated as follows: if v out(rpl) (r) < 0.5 v out(rpl) (c), then v out(rpl) = v out(rpl) (c), otherwise, v out(rpl) = 0.5 v out(rpl) (c) + v out(rpl) (r). lower voltage input the application circuit shown here can be easily modified to work with 5.5 v to 12 v input voltages. oscillation frequency should be set at 200 khz and increase the output capacitance to 660 f on the 5 v output to maintain stable performance up to 2 a of load current. operation on the 3.3 v supply will not be affect ed by this reduced input voltage. vishay siliconix maintains worldwide manufacturing capability. pro ducts may be manufactured at on e of several qualified locatio ns. reliability data for silicon tech- nology and package reliability represent a composite of all qua lified locations. for related documents such as package/tape dra wings, part marking, and reliability data, see www.vishay.com/ppg?70190 . l v out v in(max) - v out v in(max) ( f ) i out ( lir ) i lpeak i out v out v in(max) - v out (2)(f)(l) v in(max) + c f v ref v out r cs (2)( )(gbwp) esr cf v out r cs v ref v out(rpl) i lpp(max) esr cf 1 2xf cf + x x + x v out(rpl) (c) (4) 10 - 4 (l) r cs 2 c f 1 v out 1 v in - v out volts v out(rpl) (r) (0.02) esr cf r cs volts
l 1 ? c ? a 1 0.076 28 15 1 ? b ? e c l m s 0.12 a b c 14 e 1 e ? a ? b seating plane seating plane gauge plane 0.25 r c d a 2 a package information vishay siliconix document number: 72810 28-jan-04 www.vishay.com 1 ssop: 28-lead (5.3 mm) (power ic only) millimeters dim min nom max a 1.73 1.88 1.99 a 1 0.05 0.13 0.21 a 2 1.68 1.75 1.78 b 0.25 0.30 0.38 c 0.09 0.15 0.20 d 10.07 10.20 10.33 e 7.60 7.80 8.00 e 1 5.20 5.30 5.40 e 0.65 bsc l 0.63 0.75 0.95 l 1 1.25 bsc r 0.09 0.15 ? ? ? 0 4 8 ecn: s-40080?rev. a, 02-feb-04 dwg: 5915
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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